module transfer(
  input        io_systemclk,
  input        io_systemRstn,
  input  [1:0] io_cardio_card_group_data,
  input        io_cardio_card_group_cmd,
  output       io_cardio_group_card_state,
  output [7:0] io_cardio_group_card_result,
  output [1:0] io_emitterio_fpga_cim_data,
  output       io_emitterio_fpga_cim_cmd,
  input        io_emitterio_cim_fpga_state,
  input  [7:0] io_emitterio_cim_fpga_result
);
  wire  systemRst = ~io_systemRstn; // @[transfer.scala 31:19]
  reg [1:0] io_emitterio_fpga_cim_data_r; // @[Reg.scala 28:20]
  reg  io_emitterio_fpga_cim_cmd_r; // @[Reg.scala 28:20]
  reg [7:0] io_cardio_group_card_result_r; // @[Reg.scala 28:20]
  reg  io_cardio_group_card_state_r; // @[Reg.scala 28:20]
  assign io_cardio_group_card_state = io_cardio_group_card_state_r; // @[transfer.scala 36:34]
  assign io_cardio_group_card_result = io_cardio_group_card_result_r; // @[transfer.scala 35:34]
  assign io_emitterio_fpga_cim_data = io_emitterio_fpga_cim_data_r; // @[transfer.scala 33:32]
  assign io_emitterio_fpga_cim_cmd = io_emitterio_fpga_cim_cmd_r; // @[transfer.scala 34:32]
  always @(posedge io_systemclk) begin
    if (systemRst) begin // @[Reg.scala 28:20]
      io_emitterio_fpga_cim_data_r <= 2'h0; // @[Reg.scala 28:20]
    end else begin
      io_emitterio_fpga_cim_data_r <= io_cardio_card_group_data;
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      io_emitterio_fpga_cim_cmd_r <= 1'h0; // @[Reg.scala 28:20]
    end else begin
      io_emitterio_fpga_cim_cmd_r <= io_cardio_card_group_cmd;
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      io_cardio_group_card_result_r <= 8'h0; // @[Reg.scala 28:20]
    end else begin
      io_cardio_group_card_result_r <= io_emitterio_cim_fpga_result;
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      io_cardio_group_card_state_r <= 1'h0; // @[Reg.scala 28:20]
    end else begin
      io_cardio_group_card_state_r <= io_emitterio_cim_fpga_state;
    end
  end
endmodule
module emitter(
  input        io_systemclk,
  input        io_systemRstn,
  input        io_enable,
  input  [1:0] io_emitterio_fpga_cim_data,
  input        io_emitterio_fpga_cim_cmd,
  output       io_emitterio_cim_fpga_state,
  output [7:0] io_emitterio_cim_fpga_result,
  output [1:0] io_chipio_fpga_cim_data,
  output       io_chipio_fpga_cim_cmd,
  input        io_chipio_cim_fpga_state,
  input        io_chipio_cim_fpga_clk,
  input  [7:0] io_chipio_cim_fpga_result
);
  wire  BUFG_I; // @[emitter.scala 41:22]
  wire  BUFG_O; // @[emitter.scala 41:22]
  wire  systemRst = ~io_systemRstn; // @[emitter.scala 34:19]
  reg [1:0] data; // @[Reg.scala 28:20]
  reg  cmd; // @[Reg.scala 28:20]
  reg  state; // @[Reg.scala 28:20]
  reg [7:0] result; // @[Reg.scala 28:20]
  BUFG BUFG ( // @[emitter.scala 41:22]
    .I(BUFG_I),
    .O(BUFG_O)
  );
  assign io_emitterio_cim_fpga_state = state; // @[emitter.scala 46:35]
  assign io_emitterio_cim_fpga_result = result; // @[emitter.scala 47:35]
  assign io_chipio_fpga_cim_data = data; // @[emitter.scala 38:33]
  assign io_chipio_fpga_cim_cmd = cmd; // @[emitter.scala 39:33]
  assign BUFG_I = io_chipio_cim_fpga_clk; // @[emitter.scala 42:12]
  always @(posedge io_systemclk) begin
    if (systemRst) begin // @[Reg.scala 28:20]
      data <= 2'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      data <= io_emitterio_fpga_cim_data; // @[Reg.scala 29:22]
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      cmd <= 1'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      cmd <= io_emitterio_fpga_cim_cmd; // @[Reg.scala 29:22]
    end
  end
  always @(posedge BUFG_O) begin
    if (systemRst) begin // @[Reg.scala 28:20]
      state <= 1'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      state <= io_chipio_cim_fpga_state; // @[Reg.scala 29:22]
    end
    if (systemRst) begin // @[Reg.scala 28:20]
      result <= 8'h0; // @[Reg.scala 28:20]
    end else if (io_enable) begin // @[Reg.scala 29:18]
      result <= io_chipio_cim_fpga_result; // @[Reg.scala 29:22]
    end
  end
endmodule
module group(
  input        io_systemclk,
  input        io_systemRstn,
  input  [1:0] io_cardio_card_group_data,
  input        io_cardio_card_group_cmd,
  output       io_cardio_group_card_state,
  output [7:0] io_cardio_group_card_result,
  output [1:0] io_chipio_0_fpga_cim_data,
  output       io_chipio_0_fpga_cim_cmd,
  input        io_chipio_0_cim_fpga_state,
  input        io_chipio_0_cim_fpga_clk,
  input  [7:0] io_chipio_0_cim_fpga_result,
  output [1:0] io_chipio_1_fpga_cim_data,
  output       io_chipio_1_fpga_cim_cmd,
  input        io_chipio_1_cim_fpga_state,
  input        io_chipio_1_cim_fpga_clk,
  input  [7:0] io_chipio_1_cim_fpga_result,
  output [1:0] io_chipio_2_fpga_cim_data,
  output       io_chipio_2_fpga_cim_cmd,
  input        io_chipio_2_cim_fpga_state,
  input        io_chipio_2_cim_fpga_clk,
  input  [7:0] io_chipio_2_cim_fpga_result,
  output [1:0] io_chipio_3_fpga_cim_data,
  output       io_chipio_3_fpga_cim_cmd,
  input        io_chipio_3_cim_fpga_state,
  input        io_chipio_3_cim_fpga_clk,
  input  [7:0] io_chipio_3_cim_fpga_result,
  output [1:0] io_chipio_4_fpga_cim_data,
  output       io_chipio_4_fpga_cim_cmd,
  input        io_chipio_4_cim_fpga_state,
  input        io_chipio_4_cim_fpga_clk,
  input  [7:0] io_chipio_4_cim_fpga_result,
  output [1:0] io_chipio_5_fpga_cim_data,
  output       io_chipio_5_fpga_cim_cmd,
  input        io_chipio_5_cim_fpga_state,
  input        io_chipio_5_cim_fpga_clk,
  input  [7:0] io_chipio_5_cim_fpga_result,
  output [1:0] io_chipio_6_fpga_cim_data,
  output       io_chipio_6_fpga_cim_cmd,
  input        io_chipio_6_cim_fpga_state,
  input        io_chipio_6_cim_fpga_clk,
  input  [7:0] io_chipio_6_cim_fpga_result,
  output [1:0] io_chipio_7_fpga_cim_data,
  output       io_chipio_7_fpga_cim_cmd,
  input        io_chipio_7_cim_fpga_state,
  input        io_chipio_7_cim_fpga_clk,
  input  [7:0] io_chipio_7_cim_fpga_result,
  output [1:0] io_chipio_8_fpga_cim_data,
  output       io_chipio_8_fpga_cim_cmd,
  input        io_chipio_8_cim_fpga_state,
  input        io_chipio_8_cim_fpga_clk,
  input  [7:0] io_chipio_8_cim_fpga_result,
  output [1:0] io_chipio_9_fpga_cim_data,
  output       io_chipio_9_fpga_cim_cmd,
  input        io_chipio_9_cim_fpga_state,
  input        io_chipio_9_cim_fpga_clk,
  input  [7:0] io_chipio_9_cim_fpga_result,
  output [1:0] io_chipio_10_fpga_cim_data,
  output       io_chipio_10_fpga_cim_cmd,
  input        io_chipio_10_cim_fpga_state,
  input        io_chipio_10_cim_fpga_clk,
  input  [7:0] io_chipio_10_cim_fpga_result,
  output [1:0] io_chipio_11_fpga_cim_data,
  output       io_chipio_11_fpga_cim_cmd,
  input        io_chipio_11_cim_fpga_state,
  input        io_chipio_11_cim_fpga_clk,
  input  [7:0] io_chipio_11_cim_fpga_result,
  output [1:0] io_chipio_12_fpga_cim_data,
  output       io_chipio_12_fpga_cim_cmd,
  input        io_chipio_12_cim_fpga_state,
  input        io_chipio_12_cim_fpga_clk,
  input  [7:0] io_chipio_12_cim_fpga_result,
  output [1:0] io_chipio_13_fpga_cim_data,
  output       io_chipio_13_fpga_cim_cmd,
  input        io_chipio_13_cim_fpga_state,
  input        io_chipio_13_cim_fpga_clk,
  input  [7:0] io_chipio_13_cim_fpga_result,
  output [1:0] io_chipio_14_fpga_cim_data,
  output       io_chipio_14_fpga_cim_cmd,
  input        io_chipio_14_cim_fpga_state,
  input        io_chipio_14_cim_fpga_clk,
  input  [7:0] io_chipio_14_cim_fpga_result,
  output [1:0] io_chipio_15_fpga_cim_data,
  output       io_chipio_15_fpga_cim_cmd,
  input        io_chipio_15_cim_fpga_state,
  input        io_chipio_15_cim_fpga_clk,
  input  [7:0] io_chipio_15_cim_fpga_result,
  output [3:0] io_dcout_cim_dcdata,
  output       io_dcout_cim_dcvld,
  input  [3:0] io_dcin_cim_dcdata,
  input        io_dcin_cim_dcvld
);
  wire  BUFG_I; // @[group.scala 15:22]
  wire  BUFG_O; // @[group.scala 15:22]
  wire  transfer_io_systemclk; // @[group.scala 27:26]
  wire  transfer_io_systemRstn; // @[group.scala 27:26]
  wire [1:0] transfer_io_cardio_card_group_data; // @[group.scala 27:26]
  wire  transfer_io_cardio_card_group_cmd; // @[group.scala 27:26]
  wire  transfer_io_cardio_group_card_state; // @[group.scala 27:26]
  wire [7:0] transfer_io_cardio_group_card_result; // @[group.scala 27:26]
  wire [1:0] transfer_io_emitterio_fpga_cim_data; // @[group.scala 27:26]
  wire  transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 27:26]
  wire  transfer_io_emitterio_cim_fpga_state; // @[group.scala 27:26]
  wire [7:0] transfer_io_emitterio_cim_fpga_result; // @[group.scala 27:26]
  wire  emitter_io_systemclk; // @[group.scala 32:46]
  wire  emitter_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_1_io_systemclk; // @[group.scala 32:46]
  wire  emitter_1_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_1_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_1_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_1_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_1_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_1_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_1_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_1_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_1_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_1_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_1_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_2_io_systemclk; // @[group.scala 32:46]
  wire  emitter_2_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_2_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_2_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_2_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_2_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_2_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_2_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_2_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_2_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_2_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_2_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_3_io_systemclk; // @[group.scala 32:46]
  wire  emitter_3_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_3_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_3_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_3_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_3_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_3_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_3_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_3_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_3_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_3_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_3_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_4_io_systemclk; // @[group.scala 32:46]
  wire  emitter_4_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_4_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_4_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_4_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_4_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_4_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_4_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_4_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_4_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_4_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_4_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_5_io_systemclk; // @[group.scala 32:46]
  wire  emitter_5_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_5_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_5_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_5_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_5_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_5_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_5_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_5_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_5_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_5_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_5_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_6_io_systemclk; // @[group.scala 32:46]
  wire  emitter_6_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_6_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_6_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_6_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_6_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_6_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_6_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_6_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_6_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_6_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_6_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_7_io_systemclk; // @[group.scala 32:46]
  wire  emitter_7_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_7_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_7_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_7_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_7_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_7_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_7_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_7_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_7_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_7_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_7_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_8_io_systemclk; // @[group.scala 32:46]
  wire  emitter_8_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_8_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_8_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_8_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_8_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_8_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_8_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_8_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_8_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_8_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_8_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_9_io_systemclk; // @[group.scala 32:46]
  wire  emitter_9_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_9_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_9_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_9_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_9_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_9_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_9_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_9_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_9_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_9_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_9_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_10_io_systemclk; // @[group.scala 32:46]
  wire  emitter_10_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_10_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_10_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_10_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_10_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_10_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_10_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_10_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_10_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_10_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_10_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_11_io_systemclk; // @[group.scala 32:46]
  wire  emitter_11_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_11_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_11_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_11_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_11_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_11_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_11_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_11_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_11_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_11_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_11_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_12_io_systemclk; // @[group.scala 32:46]
  wire  emitter_12_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_12_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_12_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_12_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_12_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_12_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_12_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_12_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_12_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_12_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_12_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_13_io_systemclk; // @[group.scala 32:46]
  wire  emitter_13_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_13_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_13_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_13_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_13_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_13_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_13_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_13_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_13_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_13_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_13_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_14_io_systemclk; // @[group.scala 32:46]
  wire  emitter_14_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_14_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_14_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_14_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_14_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_14_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_14_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_14_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_14_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_14_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_14_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  emitter_15_io_systemclk; // @[group.scala 32:46]
  wire  emitter_15_io_systemRstn; // @[group.scala 32:46]
  wire  emitter_15_io_enable; // @[group.scala 32:46]
  wire [1:0] emitter_15_io_emitterio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_15_io_emitterio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_15_io_emitterio_cim_fpga_state; // @[group.scala 32:46]
  wire [7:0] emitter_15_io_emitterio_cim_fpga_result; // @[group.scala 32:46]
  wire [1:0] emitter_15_io_chipio_fpga_cim_data; // @[group.scala 32:46]
  wire  emitter_15_io_chipio_fpga_cim_cmd; // @[group.scala 32:46]
  wire  emitter_15_io_chipio_cim_fpga_state; // @[group.scala 32:46]
  wire  emitter_15_io_chipio_cim_fpga_clk; // @[group.scala 32:46]
  wire [7:0] emitter_15_io_chipio_cim_fpga_result; // @[group.scala 32:46]
  wire  systemRst = ~io_systemRstn; // @[group.scala 17:19]
  reg [3:0] io_dcout_cim_dcdata_REG; // @[group.scala 20:35]
  reg  io_dcout_cim_dcvld_REG; // @[group.scala 21:35]
  reg [4:0] counter; // @[group.scala 23:26]
  wire [4:0] _counter_T_2 = counter + 5'h1; // @[group.scala 24:50]
  wire  enable_array_0 = counter == 5'h1; // @[group.scala 39:35]
  wire  cim_fpga_state_list_0 = emitter_io_emitterio_cim_fpga_state & enable_array_0; // @[group.scala 33:98]
  wire  enable_array_1 = counter == 5'h2; // @[group.scala 39:35]
  wire  cim_fpga_state_list_1 = emitter_1_io_emitterio_cim_fpga_state & enable_array_1; // @[group.scala 33:98]
  wire  enable_array_2 = counter == 5'h3; // @[group.scala 39:35]
  wire  cim_fpga_state_list_2 = emitter_2_io_emitterio_cim_fpga_state & enable_array_2; // @[group.scala 33:98]
  wire  enable_array_3 = counter == 5'h4; // @[group.scala 39:35]
  wire  cim_fpga_state_list_3 = emitter_3_io_emitterio_cim_fpga_state & enable_array_3; // @[group.scala 33:98]
  wire  enable_array_4 = counter == 5'h5; // @[group.scala 39:35]
  wire  cim_fpga_state_list_4 = emitter_4_io_emitterio_cim_fpga_state & enable_array_4; // @[group.scala 33:98]
  wire  enable_array_5 = counter == 5'h6; // @[group.scala 39:35]
  wire  cim_fpga_state_list_5 = emitter_5_io_emitterio_cim_fpga_state & enable_array_5; // @[group.scala 33:98]
  wire  enable_array_6 = counter == 5'h7; // @[group.scala 39:35]
  wire  cim_fpga_state_list_6 = emitter_6_io_emitterio_cim_fpga_state & enable_array_6; // @[group.scala 33:98]
  wire  enable_array_7 = counter == 5'h8; // @[group.scala 39:35]
  wire  cim_fpga_state_list_7 = emitter_7_io_emitterio_cim_fpga_state & enable_array_7; // @[group.scala 33:98]
  wire  enable_array_8 = counter == 5'h9; // @[group.scala 39:35]
  wire  cim_fpga_state_list_8 = emitter_8_io_emitterio_cim_fpga_state & enable_array_8; // @[group.scala 33:98]
  wire  enable_array_9 = counter == 5'ha; // @[group.scala 39:35]
  wire  cim_fpga_state_list_9 = emitter_9_io_emitterio_cim_fpga_state & enable_array_9; // @[group.scala 33:98]
  wire  enable_array_10 = counter == 5'hb; // @[group.scala 39:35]
  wire  cim_fpga_state_list_10 = emitter_10_io_emitterio_cim_fpga_state & enable_array_10; // @[group.scala 33:98]
  wire  enable_array_11 = counter == 5'hc; // @[group.scala 39:35]
  wire  cim_fpga_state_list_11 = emitter_11_io_emitterio_cim_fpga_state & enable_array_11; // @[group.scala 33:98]
  wire  enable_array_12 = counter == 5'hd; // @[group.scala 39:35]
  wire  cim_fpga_state_list_12 = emitter_12_io_emitterio_cim_fpga_state & enable_array_12; // @[group.scala 33:98]
  wire  enable_array_13 = counter == 5'he; // @[group.scala 39:35]
  wire  cim_fpga_state_list_13 = emitter_13_io_emitterio_cim_fpga_state & enable_array_13; // @[group.scala 33:98]
  wire  enable_array_14 = counter == 5'hf; // @[group.scala 39:35]
  wire  cim_fpga_state_list_14 = emitter_14_io_emitterio_cim_fpga_state & enable_array_14; // @[group.scala 33:98]
  wire  enable_array_15 = counter == 5'h10; // @[group.scala 39:35]
  wire  cim_fpga_state_list_15 = emitter_15_io_emitterio_cim_fpga_state & enable_array_15; // @[group.scala 33:98]
  wire [7:0] _cim_fpga_result_list_T_1 = enable_array_0 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_0 = emitter_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_1; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_3 = enable_array_1 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_1 = emitter_1_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_3; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_5 = enable_array_2 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_2 = emitter_2_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_5; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_7 = enable_array_3 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_3 = emitter_3_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_7; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_9 = enable_array_4 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_4 = emitter_4_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_9; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_11 = enable_array_5 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_5 = emitter_5_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_11; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_13 = enable_array_6 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_6 = emitter_6_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_13; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_15 = enable_array_7 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_7 = emitter_7_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_15; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_17 = enable_array_8 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_8 = emitter_8_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_17; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_19 = enable_array_9 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_9 = emitter_9_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_19; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_21 = enable_array_10 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_10 = emitter_10_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_21; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_23 = enable_array_11 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_11 = emitter_11_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_23; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_25 = enable_array_12 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_12 = emitter_12_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_25; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_27 = enable_array_13 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_13 = emitter_13_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_27; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_29 = enable_array_14 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_14 = emitter_14_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_29; // @[group.scala 34:99]
  wire [7:0] _cim_fpga_result_list_T_31 = enable_array_15 ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] cim_fpga_result_list_15 = emitter_15_io_emitterio_cim_fpga_result & _cim_fpga_result_list_T_31; // @[group.scala 34:99]
  wire [7:0] _T_15 = cim_fpga_result_list_0 | cim_fpga_result_list_1; // @[group.scala 36:72]
  wire [7:0] _T_16 = _T_15 | cim_fpga_result_list_2; // @[group.scala 36:72]
  wire [7:0] _T_17 = _T_16 | cim_fpga_result_list_3; // @[group.scala 36:72]
  wire [7:0] _T_18 = _T_17 | cim_fpga_result_list_4; // @[group.scala 36:72]
  wire [7:0] _T_19 = _T_18 | cim_fpga_result_list_5; // @[group.scala 36:72]
  wire [7:0] _T_20 = _T_19 | cim_fpga_result_list_6; // @[group.scala 36:72]
  wire [7:0] _T_21 = _T_20 | cim_fpga_result_list_7; // @[group.scala 36:72]
  wire [7:0] _T_22 = _T_21 | cim_fpga_result_list_8; // @[group.scala 36:72]
  wire [7:0] _T_23 = _T_22 | cim_fpga_result_list_9; // @[group.scala 36:72]
  wire [7:0] _T_24 = _T_23 | cim_fpga_result_list_10; // @[group.scala 36:72]
  wire [7:0] _T_25 = _T_24 | cim_fpga_result_list_11; // @[group.scala 36:72]
  wire [7:0] _T_26 = _T_25 | cim_fpga_result_list_12; // @[group.scala 36:72]
  wire [7:0] _T_27 = _T_26 | cim_fpga_result_list_13; // @[group.scala 36:72]
  wire [7:0] _T_28 = _T_27 | cim_fpga_result_list_14; // @[group.scala 36:72]
  BUFG BUFG ( // @[group.scala 15:22]
    .I(BUFG_I),
    .O(BUFG_O)
  );
  transfer transfer ( // @[group.scala 27:26]
    .io_systemclk(transfer_io_systemclk),
    .io_systemRstn(transfer_io_systemRstn),
    .io_cardio_card_group_data(transfer_io_cardio_card_group_data),
    .io_cardio_card_group_cmd(transfer_io_cardio_card_group_cmd),
    .io_cardio_group_card_state(transfer_io_cardio_group_card_state),
    .io_cardio_group_card_result(transfer_io_cardio_group_card_result),
    .io_emitterio_fpga_cim_data(transfer_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(transfer_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(transfer_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(transfer_io_emitterio_cim_fpga_result)
  );
  emitter emitter ( // @[group.scala 32:46]
    .io_systemclk(emitter_io_systemclk),
    .io_systemRstn(emitter_io_systemRstn),
    .io_enable(emitter_io_enable),
    .io_emitterio_fpga_cim_data(emitter_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_io_chipio_cim_fpga_result)
  );
  emitter emitter_1 ( // @[group.scala 32:46]
    .io_systemclk(emitter_1_io_systemclk),
    .io_systemRstn(emitter_1_io_systemRstn),
    .io_enable(emitter_1_io_enable),
    .io_emitterio_fpga_cim_data(emitter_1_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_1_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_1_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_1_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_1_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_1_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_1_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_1_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_1_io_chipio_cim_fpga_result)
  );
  emitter emitter_2 ( // @[group.scala 32:46]
    .io_systemclk(emitter_2_io_systemclk),
    .io_systemRstn(emitter_2_io_systemRstn),
    .io_enable(emitter_2_io_enable),
    .io_emitterio_fpga_cim_data(emitter_2_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_2_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_2_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_2_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_2_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_2_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_2_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_2_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_2_io_chipio_cim_fpga_result)
  );
  emitter emitter_3 ( // @[group.scala 32:46]
    .io_systemclk(emitter_3_io_systemclk),
    .io_systemRstn(emitter_3_io_systemRstn),
    .io_enable(emitter_3_io_enable),
    .io_emitterio_fpga_cim_data(emitter_3_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_3_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_3_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_3_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_3_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_3_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_3_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_3_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_3_io_chipio_cim_fpga_result)
  );
  emitter emitter_4 ( // @[group.scala 32:46]
    .io_systemclk(emitter_4_io_systemclk),
    .io_systemRstn(emitter_4_io_systemRstn),
    .io_enable(emitter_4_io_enable),
    .io_emitterio_fpga_cim_data(emitter_4_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_4_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_4_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_4_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_4_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_4_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_4_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_4_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_4_io_chipio_cim_fpga_result)
  );
  emitter emitter_5 ( // @[group.scala 32:46]
    .io_systemclk(emitter_5_io_systemclk),
    .io_systemRstn(emitter_5_io_systemRstn),
    .io_enable(emitter_5_io_enable),
    .io_emitterio_fpga_cim_data(emitter_5_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_5_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_5_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_5_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_5_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_5_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_5_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_5_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_5_io_chipio_cim_fpga_result)
  );
  emitter emitter_6 ( // @[group.scala 32:46]
    .io_systemclk(emitter_6_io_systemclk),
    .io_systemRstn(emitter_6_io_systemRstn),
    .io_enable(emitter_6_io_enable),
    .io_emitterio_fpga_cim_data(emitter_6_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_6_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_6_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_6_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_6_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_6_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_6_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_6_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_6_io_chipio_cim_fpga_result)
  );
  emitter emitter_7 ( // @[group.scala 32:46]
    .io_systemclk(emitter_7_io_systemclk),
    .io_systemRstn(emitter_7_io_systemRstn),
    .io_enable(emitter_7_io_enable),
    .io_emitterio_fpga_cim_data(emitter_7_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_7_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_7_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_7_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_7_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_7_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_7_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_7_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_7_io_chipio_cim_fpga_result)
  );
  emitter emitter_8 ( // @[group.scala 32:46]
    .io_systemclk(emitter_8_io_systemclk),
    .io_systemRstn(emitter_8_io_systemRstn),
    .io_enable(emitter_8_io_enable),
    .io_emitterio_fpga_cim_data(emitter_8_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_8_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_8_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_8_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_8_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_8_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_8_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_8_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_8_io_chipio_cim_fpga_result)
  );
  emitter emitter_9 ( // @[group.scala 32:46]
    .io_systemclk(emitter_9_io_systemclk),
    .io_systemRstn(emitter_9_io_systemRstn),
    .io_enable(emitter_9_io_enable),
    .io_emitterio_fpga_cim_data(emitter_9_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_9_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_9_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_9_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_9_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_9_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_9_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_9_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_9_io_chipio_cim_fpga_result)
  );
  emitter emitter_10 ( // @[group.scala 32:46]
    .io_systemclk(emitter_10_io_systemclk),
    .io_systemRstn(emitter_10_io_systemRstn),
    .io_enable(emitter_10_io_enable),
    .io_emitterio_fpga_cim_data(emitter_10_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_10_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_10_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_10_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_10_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_10_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_10_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_10_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_10_io_chipio_cim_fpga_result)
  );
  emitter emitter_11 ( // @[group.scala 32:46]
    .io_systemclk(emitter_11_io_systemclk),
    .io_systemRstn(emitter_11_io_systemRstn),
    .io_enable(emitter_11_io_enable),
    .io_emitterio_fpga_cim_data(emitter_11_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_11_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_11_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_11_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_11_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_11_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_11_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_11_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_11_io_chipio_cim_fpga_result)
  );
  emitter emitter_12 ( // @[group.scala 32:46]
    .io_systemclk(emitter_12_io_systemclk),
    .io_systemRstn(emitter_12_io_systemRstn),
    .io_enable(emitter_12_io_enable),
    .io_emitterio_fpga_cim_data(emitter_12_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_12_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_12_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_12_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_12_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_12_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_12_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_12_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_12_io_chipio_cim_fpga_result)
  );
  emitter emitter_13 ( // @[group.scala 32:46]
    .io_systemclk(emitter_13_io_systemclk),
    .io_systemRstn(emitter_13_io_systemRstn),
    .io_enable(emitter_13_io_enable),
    .io_emitterio_fpga_cim_data(emitter_13_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_13_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_13_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_13_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_13_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_13_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_13_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_13_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_13_io_chipio_cim_fpga_result)
  );
  emitter emitter_14 ( // @[group.scala 32:46]
    .io_systemclk(emitter_14_io_systemclk),
    .io_systemRstn(emitter_14_io_systemRstn),
    .io_enable(emitter_14_io_enable),
    .io_emitterio_fpga_cim_data(emitter_14_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_14_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_14_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_14_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_14_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_14_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_14_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_14_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_14_io_chipio_cim_fpga_result)
  );
  emitter emitter_15 ( // @[group.scala 32:46]
    .io_systemclk(emitter_15_io_systemclk),
    .io_systemRstn(emitter_15_io_systemRstn),
    .io_enable(emitter_15_io_enable),
    .io_emitterio_fpga_cim_data(emitter_15_io_emitterio_fpga_cim_data),
    .io_emitterio_fpga_cim_cmd(emitter_15_io_emitterio_fpga_cim_cmd),
    .io_emitterio_cim_fpga_state(emitter_15_io_emitterio_cim_fpga_state),
    .io_emitterio_cim_fpga_result(emitter_15_io_emitterio_cim_fpga_result),
    .io_chipio_fpga_cim_data(emitter_15_io_chipio_fpga_cim_data),
    .io_chipio_fpga_cim_cmd(emitter_15_io_chipio_fpga_cim_cmd),
    .io_chipio_cim_fpga_state(emitter_15_io_chipio_cim_fpga_state),
    .io_chipio_cim_fpga_clk(emitter_15_io_chipio_cim_fpga_clk),
    .io_chipio_cim_fpga_result(emitter_15_io_chipio_cim_fpga_result)
  );
  assign io_cardio_group_card_state = transfer_io_cardio_group_card_state; // @[group.scala 30:21]
  assign io_cardio_group_card_result = transfer_io_cardio_group_card_result; // @[group.scala 30:21]
  assign io_chipio_0_fpga_cim_data = emitter_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_0_fpga_cim_cmd = emitter_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_1_fpga_cim_data = emitter_1_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_1_fpga_cim_cmd = emitter_1_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_2_fpga_cim_data = emitter_2_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_2_fpga_cim_cmd = emitter_2_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_3_fpga_cim_data = emitter_3_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_3_fpga_cim_cmd = emitter_3_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_4_fpga_cim_data = emitter_4_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_4_fpga_cim_cmd = emitter_4_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_5_fpga_cim_data = emitter_5_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_5_fpga_cim_cmd = emitter_5_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_6_fpga_cim_data = emitter_6_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_6_fpga_cim_cmd = emitter_6_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_7_fpga_cim_data = emitter_7_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_7_fpga_cim_cmd = emitter_7_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_8_fpga_cim_data = emitter_8_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_8_fpga_cim_cmd = emitter_8_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_9_fpga_cim_data = emitter_9_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_9_fpga_cim_cmd = emitter_9_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_10_fpga_cim_data = emitter_10_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_10_fpga_cim_cmd = emitter_10_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_11_fpga_cim_data = emitter_11_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_11_fpga_cim_cmd = emitter_11_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_12_fpga_cim_data = emitter_12_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_12_fpga_cim_cmd = emitter_12_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_13_fpga_cim_data = emitter_13_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_13_fpga_cim_cmd = emitter_13_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_14_fpga_cim_data = emitter_14_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_14_fpga_cim_cmd = emitter_14_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_chipio_15_fpga_cim_data = emitter_15_io_chipio_fpga_cim_data; // @[group.scala 45:25]
  assign io_chipio_15_fpga_cim_cmd = emitter_15_io_chipio_fpga_cim_cmd; // @[group.scala 45:25]
  assign io_dcout_cim_dcdata = io_dcout_cim_dcdata_REG; // @[group.scala 20:25]
  assign io_dcout_cim_dcvld = io_dcout_cim_dcvld_REG; // @[group.scala 21:25]
  assign BUFG_I = io_systemclk; // @[group.scala 16:12]
  assign transfer_io_systemclk = io_systemclk; // @[group.scala 28:24]
  assign transfer_io_systemRstn = io_systemRstn; // @[group.scala 29:25]
  assign transfer_io_cardio_card_group_data = io_cardio_card_group_data; // @[group.scala 30:21]
  assign transfer_io_cardio_card_group_cmd = io_cardio_card_group_cmd; // @[group.scala 30:21]
  assign transfer_io_emitterio_cim_fpga_state = cim_fpga_state_list_0 | cim_fpga_state_list_1 | cim_fpga_state_list_2 |
    cim_fpga_state_list_3 | cim_fpga_state_list_4 | cim_fpga_state_list_5 | cim_fpga_state_list_6 |
    cim_fpga_state_list_7 | cim_fpga_state_list_8 | cim_fpga_state_list_9 | cim_fpga_state_list_10 |
    cim_fpga_state_list_11 | cim_fpga_state_list_12 | cim_fpga_state_list_13 | cim_fpga_state_list_14 |
    cim_fpga_state_list_15; // @[group.scala 35:70]
  assign transfer_io_emitterio_cim_fpga_result = _T_28 | cim_fpga_result_list_15; // @[group.scala 36:72]
  assign emitter_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_io_enable = counter == 5'h1; // @[group.scala 39:35]
  assign emitter_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_io_chipio_cim_fpga_state = io_chipio_0_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_io_chipio_cim_fpga_clk = io_chipio_0_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_io_chipio_cim_fpga_result = io_chipio_0_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_1_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_1_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_1_io_enable = counter == 5'h2; // @[group.scala 39:35]
  assign emitter_1_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_1_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_1_io_chipio_cim_fpga_state = io_chipio_1_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_1_io_chipio_cim_fpga_clk = io_chipio_1_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_1_io_chipio_cim_fpga_result = io_chipio_1_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_2_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_2_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_2_io_enable = counter == 5'h3; // @[group.scala 39:35]
  assign emitter_2_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_2_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_2_io_chipio_cim_fpga_state = io_chipio_2_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_2_io_chipio_cim_fpga_clk = io_chipio_2_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_2_io_chipio_cim_fpga_result = io_chipio_2_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_3_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_3_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_3_io_enable = counter == 5'h4; // @[group.scala 39:35]
  assign emitter_3_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_3_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_3_io_chipio_cim_fpga_state = io_chipio_3_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_3_io_chipio_cim_fpga_clk = io_chipio_3_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_3_io_chipio_cim_fpga_result = io_chipio_3_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_4_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_4_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_4_io_enable = counter == 5'h5; // @[group.scala 39:35]
  assign emitter_4_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_4_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_4_io_chipio_cim_fpga_state = io_chipio_4_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_4_io_chipio_cim_fpga_clk = io_chipio_4_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_4_io_chipio_cim_fpga_result = io_chipio_4_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_5_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_5_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_5_io_enable = counter == 5'h6; // @[group.scala 39:35]
  assign emitter_5_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_5_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_5_io_chipio_cim_fpga_state = io_chipio_5_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_5_io_chipio_cim_fpga_clk = io_chipio_5_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_5_io_chipio_cim_fpga_result = io_chipio_5_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_6_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_6_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_6_io_enable = counter == 5'h7; // @[group.scala 39:35]
  assign emitter_6_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_6_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_6_io_chipio_cim_fpga_state = io_chipio_6_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_6_io_chipio_cim_fpga_clk = io_chipio_6_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_6_io_chipio_cim_fpga_result = io_chipio_6_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_7_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_7_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_7_io_enable = counter == 5'h8; // @[group.scala 39:35]
  assign emitter_7_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_7_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_7_io_chipio_cim_fpga_state = io_chipio_7_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_7_io_chipio_cim_fpga_clk = io_chipio_7_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_7_io_chipio_cim_fpga_result = io_chipio_7_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_8_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_8_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_8_io_enable = counter == 5'h9; // @[group.scala 39:35]
  assign emitter_8_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_8_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_8_io_chipio_cim_fpga_state = io_chipio_8_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_8_io_chipio_cim_fpga_clk = io_chipio_8_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_8_io_chipio_cim_fpga_result = io_chipio_8_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_9_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_9_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_9_io_enable = counter == 5'ha; // @[group.scala 39:35]
  assign emitter_9_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_9_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_9_io_chipio_cim_fpga_state = io_chipio_9_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_9_io_chipio_cim_fpga_clk = io_chipio_9_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_9_io_chipio_cim_fpga_result = io_chipio_9_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_10_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_10_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_10_io_enable = counter == 5'hb; // @[group.scala 39:35]
  assign emitter_10_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_10_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_10_io_chipio_cim_fpga_state = io_chipio_10_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_10_io_chipio_cim_fpga_clk = io_chipio_10_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_10_io_chipio_cim_fpga_result = io_chipio_10_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_11_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_11_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_11_io_enable = counter == 5'hc; // @[group.scala 39:35]
  assign emitter_11_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_11_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_11_io_chipio_cim_fpga_state = io_chipio_11_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_11_io_chipio_cim_fpga_clk = io_chipio_11_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_11_io_chipio_cim_fpga_result = io_chipio_11_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_12_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_12_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_12_io_enable = counter == 5'hd; // @[group.scala 39:35]
  assign emitter_12_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_12_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_12_io_chipio_cim_fpga_state = io_chipio_12_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_12_io_chipio_cim_fpga_clk = io_chipio_12_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_12_io_chipio_cim_fpga_result = io_chipio_12_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_13_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_13_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_13_io_enable = counter == 5'he; // @[group.scala 39:35]
  assign emitter_13_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_13_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_13_io_chipio_cim_fpga_state = io_chipio_13_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_13_io_chipio_cim_fpga_clk = io_chipio_13_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_13_io_chipio_cim_fpga_result = io_chipio_13_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_14_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_14_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_14_io_enable = counter == 5'hf; // @[group.scala 39:35]
  assign emitter_14_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_14_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_14_io_chipio_cim_fpga_state = io_chipio_14_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_14_io_chipio_cim_fpga_clk = io_chipio_14_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_14_io_chipio_cim_fpga_result = io_chipio_14_cim_fpga_result; // @[group.scala 45:25]
  assign emitter_15_io_systemclk = io_systemclk; // @[group.scala 40:28]
  assign emitter_15_io_systemRstn = io_systemRstn; // @[group.scala 41:29]
  assign emitter_15_io_enable = counter == 5'h10; // @[group.scala 39:35]
  assign emitter_15_io_emitterio_fpga_cim_data = transfer_io_emitterio_fpga_cim_data; // @[group.scala 43:41]
  assign emitter_15_io_emitterio_fpga_cim_cmd = transfer_io_emitterio_fpga_cim_cmd; // @[group.scala 42:41]
  assign emitter_15_io_chipio_cim_fpga_state = io_chipio_15_cim_fpga_state; // @[group.scala 45:25]
  assign emitter_15_io_chipio_cim_fpga_clk = io_chipio_15_cim_fpga_clk; // @[group.scala 45:25]
  assign emitter_15_io_chipio_cim_fpga_result = io_chipio_15_cim_fpga_result; // @[group.scala 45:25]
  always @(posedge BUFG_O) begin
    io_dcout_cim_dcdata_REG <= io_dcin_cim_dcdata; // @[group.scala 20:35]
    io_dcout_cim_dcvld_REG <= io_dcin_cim_dcvld; // @[group.scala 21:35]
    if (systemRst) begin // @[group.scala 23:26]
      counter <= 5'h0; // @[group.scala 23:26]
    end else if (counter < 5'h10) begin // @[group.scala 24:19]
      counter <= _counter_T_2;
    end else begin
      counter <= 5'h0;
    end
  end
endmodule
